1. Field of Invention
The present invention relates to a programmable phase-locked loop circuit implementable as, for example, an integrated circuit on a semiconductor substrate, and also to a method of programming the same without requiring different timing elements to be switched into or within the loom filter in order to program its operation over a range of stable operating frequencies.
2. Brief Description of the Prior Art
Phase-locked loop (PLL) circuits are commonly used in a wide variety of electronic systems. In frequency synthesis applications, phase-locked loop circuits are employed to ensure precision and stability. Phase-locked loons in such applications function fundamentally by receiving a predetermined reference frequency from a precision crystal and providing a locked output frequency which is a predetermined multiple of the reference frequency. A phase detector is typically used to compare the frequency of the reference with the locked output frequency after having been divided by the predetermined factor. The phase detector produces a control signal which is proportional to an error between the two frequencies being compared. The control signal is typically filtered by a loop filter to derive a voltage for controlling a voltage controlled oscillator. The voltage controlled oscillator provides the locked output frequency. A frequency divider circuit is coupled between the voltage controlled oscillator and the phase detector to complete a closed circuit loop. In general, the function of the loop filter is to permit fast locking of the cutout frequency while avoiding frequency instability problems during steady state operation.
Phase-locked loop circuits are also commonly used to synchronize data being transferred between the host processor and associated data storage and communication devices. In communication applications, phase-locked circuits are generally employed to generate a clock signal which is frequency or phase referenced to an external input signal. Depending on the particular application, the function of the clock signal will vary.
In computer systems, a recording media device controller is provided for executing CPU initiated commands to various recording medium storage devices, e.g., hard or floppy disk systems. This includes writing properly formatted serial data onto the magnetic disk and accurately recovering data therefrom. Data written onto a disk consists of logic ones and zeros which are written at a particular data rate. In order to accurately read data from the disk, the data rate of the signal being read must be known. This process is facilitated by encoding the data being written onto the disk so that the signals written onto the disk include clock information as well as data information. A variety of encoding schemes have been developed for encoding clock and data signals. U.S. Pat. No. 4,808,884 discloses one common encoding scheme, in which data is encoded on a disk in a modified frequency modulation (MFM) format. The MFM signal actually recorded onto the disk during write operations is a digital signal derived from the original non-return-to-zero (NRZ) data stream and a synchronized clock signal.
Although the disk rate has a known ideal value, the actual clock rate of the data will vary from the ideal value due to several factors. These factors include variations in the speed that the data track moves past the read head of the disk drive system. Causes of such speed variations include eccentricity and warping of the circular data tracks. In addition to variations in the actual data rate, the timing of the encoded pulses read from a disk typically deviate from the ideal due to (i) high frequency noise at the read head and (ii) a shifting of bit positions due to the magnetic field of adjacent bits of opposite polarity. The cumulative effect of noise and peak shifting results in random jitter (i.e. movement of transition pulses from their ideal positions), which is unrelated to variations in the data rate. Since the clock is recovered by reading the encoded pulses, the jitter can adversely affect the recovery of the clock signals.
Due to the various factors described above, the clock rate of recorded data must be determined by analyzing the read data and generating the clock and window signals at the appropriate frequency in order to track the data. During disk drive read operations, encoded transition pulses are read and the clock signal is recovered by a phase-Locked loop clock recovery circuit driven by the encoded transition pulses read from the disk.
In general, the phase-locked loop clock recovery circuit includes a voltage controlled oscillator employed to generate the clock signals. The output of the oscillator is applied to a phase detector where its phase is compared to the phase of the input signal (i.e. read transition pulses). The output of the phase detector is a signal with low frequency components proportional to the phase error and high frequency components resulting from bit jitter. The output of the phase detector is applied to a low pass filter which eliminates the high frequency components resulting from bit jitter, and ensures stability within the closed loop. The output of the filter is a control voltage which is applied to the oscillator to control its output frequency. The recovered clock signal from the phase-locked loop clock recovery circuit is then used to synchronize the read transition pulses, and then decode the synchronized transition pulses to produce NRZ data in a manner well known in the art.
While phase-locked loop circuits have performed generally well in read and write channels of recording media device controllers, recent developments have created significant challenges to their performance. For example, in recording media devices permitting "zone-bit" recording, the magnetic recording disk is divided up into different recording zones, each disposed about its center of rotation at a different radius. As the disk rotates at an essentially constant angular frequency under the control of a PLL drive circuit, the relative tangential velocity of the rotating disk past the write and read heads is greatest for the recording zones disposed at the greatest radial distance away from the center of rotation. Consequently, data can be written onto and read from the outer recording zones at substantial higher data rates which are proportional to the radial distance of each zone. As a result, the information storage capacity of disks employing zone bit recording can be greatly increased.
To achieve such high density recording, the write channel of the recording media controller must be capable of generating a plurality of clock signals for use with the data encoder. Each clock signal must have a frequency which is a function of the radial distance of the recording zone. Typically, this is achieved using a PLL frequency synthesizer which is programmed to generate a different clock signal for each recording zone on the disk thereof.
Similarly, the read channel of the recording media controller must be capable of recovering the clock signal from each encoded signal read from the disk. This is typically achieved using a PLL clock recovery circuit operating at about the frequency used to encode the data onto each disk recording zone during data writing operations. To ensure stability during steady state operation, the loop filter of the PLL frequency synthesizer and the PLL clock recovery circuit must be programmed for each new operating frequency which is automatically selected as the write and read heads move from recording zone to recording zone. In prior art phase-locked loop designs, this has typically involved dynamically switching resistive and/or capacitive elements into and out of the loop filter network under computer control. Often, a resistive network external to the recording media controller is employed for this purpose.
While this prior art approach to programming the loop-filter of phase locked loop circuits has permitted generally acceptable system performance even within zone-bit recording systems, it suffers from several significant shortcomings and drawbacks.
In particular, changing the time constants of the loop filter by dynamically switching resistive and/or capacitive elements presents disadvantages in terms of switching filter components, controller design and operation, and associated noise pickup. In addition, as the available discrete filter components have standard fixed values, the resulting PLL circuits are characterized by granular transfer functions even when using expensive high precision low tolerance components.
Thus, there is a great need in the art for a phase-locked loop circuit which can be programmed without the accompanying shortcomings and drawbacks of prior art techniques.